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Consider the following code (implemented exactly as described): reg A, B, ...
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Consider the following code (implemented exactly as described):
reg A, B, C;always@(posedge clock) A <= B;always@(posedge clock)
B <= (A | C) & B;always@(posedge clock)
C <= A;The minimum and maximum delays between each set of successive gates are marked as #(min: typical: max) ns and are marked on the output node of the driving gate. (Remember the timing equations are ≤ and ≥ constraints). You also need the following:
- T_setup = #(1 : 1 : 2) ns.
- T_hold = #(1: 1 :2) ns.
- T_skew = #(1: 1 : 1) ns for the clock.
- T_clock-Q = #(2 : 3 : 5) ns.
- T_logic = #(1 : 2 : 3) ns for each and every logic gate from any input to any output.
Is there potential for a hold violation? T/F
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