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If the following logic is built exactly as described, indicate a test vector that sensitizes a stuck-at-1 fault at g and propagates it to the output h. If the value of a particular input does not matter, indicate it as ‘x’ – don’t care.
wire a, b, c, d, e, f, g, h;
assign f = a ? b : c;assign g = d ^ f;assign h = e & g;