Turn registers into LFSRS.  Run functional vectors through the chip and collect the results as signatures.

Build registers as scan chains. Generate random vectors off chip, load them in, operate the chip for one cycle and collect the results.

Turn registers into LFSRs.  Alternate their use between producing pseudorandom sequences and collecting a signature.  Inspect the signatures for correctness.

Turn registers into LFSRs.  Load random vectors into the logic, and after each cycle load out the observed logic response.