In a DRAM, the row and column addresses are sent separately on a single shared address bus.

SRAMs support burst mode reads.

An attached SRAM can be read from inside the DUT with a statement like

always@(posedge clock) data<=Memory[Address]

A random access to a new read address is faster in an SRAM than a DRAM.

After reading from a first address in a DRAM, the content of the next address can be read faster than the content of the first address if it's in the same row.

Non-volatile memories, such as flash, are generally slower than SRAM and DRAM.