Consider the following code fragment intended for synthesis.
module top (input reset, clock, start; …)
// start indicates a new frame of data, about once every ms
…
always@(start)
begin
    reset=reset & 1’b0;
    #100 reset = reset & 1’b1;
end
leafmodule u1 (reset, clock, …);
leafmodule u2 (reset, clock, …);
endmodule
What is wrong with this code fragment.   There are SEVERAL things wrong.

Question

Consider the following code fragment intended for synthesis. 
 module top (input reset, clock, start;  …) 
 // start indicates a new frame of data, about once every ms 
 … 
 always@(start) 
   begin 
     reset=reset  & 1’b0; 
     #100 reset = reset & 1’b1; 
   end 
 leafmodule u1 (reset, clock, …); 
 leafmodule u2 (reset, clock, …); 
 endmodule 
 What is wrong with this code fragment.   There are SEVERAL things wrong.

Answer

There are unintended latches.

Answer

Precise delays, such as #100, are not synthesizable

Answer

The designer is modifying reset.  Reset should not be modified.

Answer

There is a simulation-synthesis mismatch in the combinational logic block.

Answer

The designer is inserting “glue” logic above the leaf module level, making synthesis runs long.

Crowdly

Consider the following code fragment intended for synthesis. module top (input...

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