Consider the

following code implemented exactly as described.

reg A, B, C, D;

always@(posedge

clock)

  begin

     A <= (A & B) | (C & D);

     B <= B ^ C;

     C <= A ^ D;

     D <= A ^ C;

  end

Each logic gate

has a delay of (1:2:3) (min:typ:max).

If the clock

period is 20 ns, and clock uncertainty is 1 ns, then what is the hold margin in

this design.