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Consider the following FSD:
Which code fragment best matches the FSD?
always@(posedge clock) if (!reset) state = S0; else state = next_state; always@(*) begin out = 3’b000; case (state) S0 : if (in==1’b0) begin next_state = S1; out = 3’b001; end else begin next_state=S2; out=3’n010; end S1 : next_state = S0; S2 : next_state = S0; default : next_state = S0; endcase end
always@(posedge clock) if (!reset) state = S0; else state = next_state; always@(*) begin out = 3’b000; case (state) S0 : if (in==1’b0) next_state = S1; else next_state=S2; S1 : begin next_state = S0; out = 3’b001; end S2 : begin next_state = S0; out = 3’b010; end default : next_state = S0; endcase end
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