Consider the following timing diagram. There are only two states in the FSM, S0 and S1. Design an FSM that is consistent with this timing diagram. Combinational logic delays are not included in this timing diagram.

always@(*)

case (current_state)

S0: // complete the code for S0

S1: // complete the code for S1

endcase

always@(posedge clock)

if (Reset) current_state = S0;

else current_state = next_state;