Consider the following logic exactly as described. Note the use of a latch. Cycle stealing is not enabled.

always@(clock)

begin

if (clock) A <= B;

if (clock) B <= A ^ C;

if (clock) C <= B;

end

This is synthesized with the following commands

Create_clock –name clock period 10 –waveform 0 5

Set_clock_uncertainty 1 clock

Note, t_ck-Q-min = 2 ns; t_hold=1 ns; t_su=0 ns; t_logic = 1 ns;

Is there potential for hold violations? If so what is the margin?