Without the TLB, address translation would be significantly slower.

Without the TLB, some addresses would be correctly translated but others not.

The TLB caches the results of the most recently/frequently performed address translations.

Without the TLB, address translation would not work.

The MMU knows whether a page is present in physical memory or not thanks to the "present" bit in page-table entries. 

If a process references a page that is currently stored on disk, the process makes a read syscall to read the page from disk.

If the memory image of a new process does not fit in physical memory, the process is always terminated by the OS. 

If a process references a page that is currently stored on disk, the MMU triggers a page fault, which causes the OS to map the page to a frame in physical memory.

The 3 most significant bits of a virtual memory address represent the virtual page number.

Virtual memory address 0b1 maps to physical memory address 0b1010.

Virtual memory address 0b0 maps to physical memory address 0b0.

The 6 most significant bits of a physical memory address represent the frame number.

The 4 least significant bits of a virtual memory address represent the offset.