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Estructura de Computadores (2025-26, Grado en Ingeniería del Software. Plan 2023 Grupo B, Grado en Ingeniería Informática. Plan 2023 Grupo B y Grado en Matemáticas + Ingeniería Informática. Plan 2023 Grupo B)
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Assume a full associative cache which can allocate up to 4 blocks. The next sequence of block references are generated by the processor:
Block references -->344, 1028, 518, 631, 2115, 1028, 518, 1508, 1028, 153
After the fourth reference, the state of the cache is:
cache block content block 0 --> block 344 of MM block 1 --> block 1028 of MM block 2 --> block 518 of MM block 3 --> block 631 of MM
What block of MM will be in the block 0 of the cache after the last reference (153) if the processor uses the LRU algorithm for replacement?
Assume a full associative cache which can allocate up to 4 blocks. The next sequence of block references are generated by the processor:
Block references -->314, 1004, 530, 665, 2220, 1004, 530, 1546, 1004, 125
After the fourth reference, the state of the cache is:
cache block content block 0 --> block 314 of MM block 1 --> block 1004 of MM block 2 --> block 530 of MM block 3 --> block 665 of MM
What block of MM will be in the block 1 of the cache after the last reference (125) if the processor uses the LRU algorithm for replacement?
| Block | D | TAG |
|---|---|---|
| 0xA | 0 | 75B |
| 0x5 | 0 | 55B |
| 0xD | 1 | CF8 |
Assume a full associative cache which can allocate up to 4 blocks. The next sequence of block references are generated by the processor:
Block references -->314, 1080, 566, 659, 2052, 1080, 566, 1503, 1080, 154
After the fourth reference, the state of the cache is:
cache block content block 0 --> block 314 of MM block 1 --> block 1080 of MM block 2 --> block 566 of MM block 3 --> block 659 of MM
What block of MM will be in the block 2 of the cache after the last reference (154) if the processor uses the LRU algorithm for replacement?
Assume a full associative cache which can allocate up to 4 blocks. The next sequence of block references are generated by the processor:
Block references -->381, 1053, 570, 683, 2122, 1053, 570, 1501, 1053, 168
After the fourth reference, the state of the cache is:
cache block content block 0 --> block 381 of MM block 1 --> block 1053 of MM block 2 --> block 570 of MM block 3 --> block 683 of MM
What block of MM will be in the block 3 of the cache after the last reference (168) if the processor uses the LRU algorithm for replacement?
Consider a MIPS processor with the configuration (1). The miss penalty is 17 cycles. Calculate the number of cycles of the memmory stage (MEM stage) when the instruction sw $3, 240($7) is executed taking into account that memory position (data) of this instruction is not found in the cache memory. We also know that there is a write buffer and it is not full.
Configurations:
(0) Write through, no-write allocate
(1) Write through, write allocate
Consider a two level cache system, where the processor generates 4722 memory references. The number of misses at level L1 is 145 and the miss rate at level L2 is 8.3%. Calculate the global miss rate in % (provide 4 decimal at least).