Consider a cache system with blocks of 2³ words, and words of 2² bytes. Calculate the block number of the main memory for the address  115419 (decimal). Note: The anwer has to be provided in decimal (advise: convert 115419 to binary, work in binary and trasform the final solution from binary to decimal).

Calculate the hit time at  L2 cache in a 1.2GHz. processor assuming that the global average memory access time is 8.5 cycles, the hit rate at L1 is 91.9%, the miss penalty at L2 is 117 cycles, the number of misses at L2 is 76 and the number of misses at L1 is 3314. Give the result in ns.

In a computer the main memory has 2⁴Mbytes, the cache has 2¹Kbytes with words of 2³ bytes and blocks of 2² words. The configuration of the cache is 4-way set associative. If the processor generates the physical address 22007197 (decimal), calculate the set of Cache where the involved block can be located. Give the result in DECIMAL.

Consider two processors P0 and P1 both using the branch not taken predition technique. The architecture of the processors uptade the PC as follow:

P0: j & jal, PC is updated in ID stage; conditional branches (beq & bne) in MEM stage

P1: j & jal, PC is uptated  in IF stage*; conditional branches (beq & bne) in EX stage

The data hazards are solved by hardware (full forwarding).

Consider a RISC-V architecture of 6 states IF, ID, EX1,EX2,M,WB where the new stage EX2 is due to the multiplication operation (mul). This operation takes two cycles. Thus, the adition/substraction/logical operations take one cycle (and calculate the result in the EX1 stage) whereas de multiplication calculte its result in EX2.

Calculate the execution time (in ns.) for the next code, assuming that the processor has a hazard unit to insert as many bubbles (stalls) as required and the next bypasses are available:

 EX1-EX1, EX2-EX1, M-EX1, RF (Register File). The cycle time is 19 ns.

or   x25, x12,x19

Calculate the execution time for the next code, assuming that the clock cycle is 8 ns., assuming that different registers hold different values (for example the content of $4 is different from the content of $8). Consider that your processor has the forwarding configuration number (1) (see the different configurations below).

add $10,$4,$29

Calculate the execution time (in ns.) for the next code, assuming that the processor has full forwarding and it inserts bubble (stalls)  in the pipeline when needed. The cycle time is 25 ns.

Consider a RISC-V architecture of 6 states IF, ID, EX1,EX2,M,WB where the new stage EX2 is due to the multiplication operation (mul). This operation takes two cycles. Thus, the adition/substraction/logical operations take one cycle (and calculate the result in the EX1 stage) whereas de multiplication calculate its result in EX2.

Calculate the execution time (in ns.) for the next code, assuming that the processor has a hazard unit to insert as many bubbles (stalls) as required and there are forwarding in the RF (Register File) only (no bypasses in the rest of stages). The cycle time is 19 ns.

or   $25, $14,$19