Transfert de données

Un mécanisme de transfert de données (ou de transfert d'opérandes) est une méthode permettant de réduire l'impact des aléas bruts sur l'exécution des instructions du pipeline. Il repose sur l'existence de chemins de données supplémentaires qui permettent d'utiliser les résultats de l'exécution des instructions avant la fin de celle-ci. Pour illustrer son fonctionnement, nous reprendrons le programme d'exemple utilisé pour l'analyse des aléas bruts.

Avant d'exécuter le programme dans le simulateur WinMIPS64, activez le mécanisme de transfert de données (dans le menu « Configurer », cochez l'option « Activer le transfert »).

Quelle est la valeur CPI pour l'exécution de programmes en pipeline avec DF activé ( CPIpipDF ) ?

What is the CPI value (CPIpip) for pipelined execution of the RAW example program ?

(It can be calculated manually or obtained from the statistics window of the WinMIPS64 simulator)

Analyze the clock cycle diagram and find the instructions that cause RAW  stall (RAW). 

Execute the RAW example program in WinMIPS simulator.

Important ! Before you execute the program in WinMIPS64 simulator, disable the data forwarding mechanism (in menu “Configure” disable the option “Enable forwarding”).

How many clock cycles were required for pipelined program execution of RAW example?

Calculate the speedup in relation to the execution of the program on the sequenced processor .

speedup = CPIseq / CPIpip

What is the speedup value?

How many instructions were  executed?

What is te CPI value for sequential program execution (CPIseq)?

R-A-W hazard

R-A-W hazard is one of the most common problems related to the pipelined and parallel instruction execution by the processor. This type of hazard occurs when the later instruction (j) requires  the results of the previous instruction (i) to be executed, but the execution of the earlier instruction (i) has not finished yet (the completion of the execution – the end of the WB phase of the instruction cycle in MIPS). If the program execution is not interfered with, it may happen that the later instruction (j) will perform operations on an incorrect argument - the correct value of the argument  for the instruction (j) is not available before the execution of the earlier instruction (i) is completed. The occurrence of this type of disturbance can be observed during the execution of the example program:

;MIPS64 RAW hazard example

Analyze that program and calculate how many clock cycles are needed to execute it on the sequential processor. Let’s assume that the execution of any instruction takes 5 clock cycles.

How many clock cycles are needed to execute this program on a sequential processor?

Number of clock cycles for pipelined execution

Before you execute the program in WinMIPS64 simulator, disable  the data forwarding mechanism

Execute the example program with WinMIPS. After the execution is finished ansfe the question: