None of the above

Serial connection

Ethernet

Bus

Parallel connection

Polling without buffering

Interrupt-driven I/O

DMA with buffering

Programmed I/O

Least Recently Used (LRU).

Optimal Replacement.

First-In, First-Out (FIFO).

Random Replacement.

Increases

Remains same

Becomes unpredictable

Decreases

A combination of multiplexers and demultiplexers will be required to connect the address lines.

The higher address lines of the CPU will be directly connected to the address lines of each RAM chip, and lower address lines will be used for chip selection.

The lower address lines of the CPU will be directly connected to the address lines of each RAM chip, and higher address lines will be used for chip selection.

All address lines of the CPU will be directly connected to the address lines of each RAM chip

Higher interrupt frequency

None of the above

Smaller RAM only

Larger monitor size

Lower instruction count or CPI

Elimination of instruction cycle phases

Reduced control memory requirement

Faster instruction execution in all cases

Easier modification of instruction set design