What is wrong with the following code fragment intended for synthesis?

reg[3:0] A;
initial

A =’4’b000 1;

always@(posedge clock)

A

Question

What is wrong with the following code fragment intended for synthesis?

reg[3:0] A; 
 initial 
 
 A =’4’b000 1; 
 
 always@(posedge clock) 
 
 A <= C;

Accepted Answer

A cannot be initialized with an initial statement, reset must be used instead

Answer

This is combinational logic feedback

Answer

A  must be declared as type wire

Answer

Nothing is wrong

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