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ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog
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Which of the following is true about semiconductor memories? Selecting incorrect answers will lead to a loss in points.
What combination of properties describe assertions as used during the verification process?Choose all that apply. Wrong answers will deduct points. Two are true.
When do you use compile – incremental in a synthesis run? Choose one.
Which of the following are true about FPGAs? Two are true. Points are taken off for incorrect answers.
Consider the following non-blocking assignments. Which choice gives the same logic?
always@(posedge clock) begin A <= in; B <= A; C <= in; end
The asynchronous FIFO still uses two receive flops in each direction on rptr and wptr. Why does this not cause problems?
When using an asynchronous FIFO, why is a gray code count sequence used when communicating the FIFO pointer address between the clock domains