You are designing a packet forwarding engine for a network router. To process each packet you have to do eight SRAM reads in sequence and one random DRAM read. Packets come in on a continuous basis – there is little dead time. The off-chip DRAM takes 60 ns to do a random access. You have these choices for the on-chip SRAM

1. A two-port (one read, one write) 10 ns SRAM

2. A three-port (two read, one write) 15 ns SRAM

3. Repeat the data in two two-port (one read, one write) 10 ns SRAMs

Which would you choose to maximize the performance per unit of area?