The code fragment below is likely to implement unintended latches?

always@(posedge clock) state <= next_state;

always@(state or A)

begin

  casex (state)

     2’b01 : if (A) next_state = 2’b10;

             else next_state = 2’b01;

     2’b10 : next_state = 2’b01;

     2’bxx : next_state = 2’b01;

  endcase

assign out = |next_state;