module fubar1 (input clock, input [1:0] H, input [2:0] B, output reg A, C);

always@(H) A = ^H;

always@(B) A=|B;

fubar2 u1 (clock, H, C);

endmodule

Question

module fubar1 (input clock, input [1:0] H, input [2:0] B, output reg A, C); 
   
 always@(H) A = ^H; 
   
 always@(B) A=|B;  
   
 fubar2 u1 (clock, H, C); 
   
 endmodule

Accepted Answer

"Wire-or" logic.

Answer

Variable declared as type reg is mis-declared.

Answer

Unsynthesizble for-loop

Answer

Variable declared as type wire is mis-declared.

Answer

Combinational logic feedback

Answer

Unsynthesizable tri-state buffer.

Answer

A logical input to the module does not appear in the module declaration list.

Answer

Unintentional latches.

Crowdly

module fubar1 (input clock, input [1:0] H, input [2:0] B, output reg A, C); ...

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