Assign common latency values to their corresponding memory types.

For the following truth table when the circuit is synthesized as Y=B'C+AB, the glitch might happen, when

With help of K-Map approach simplify the following truth table.

Important Note:

Use following symbols:

1. ( ' ) for inversion,

2. plus symbol (+) for OR operation

3. no space between variables for AND operation. E.g. BD, AC.

Write the answer in alphabetical order. Don't put spaces between the terms or addition signs.

For Example: A'C+BD'  

If the Contamination Delay is not specified we can assume it's zero.

Determine the value of Q when S = 0, R = 0.

Complete this time diagram and select the output of Q at the highlighted time moment.

In case of spatial parallelism, task is broken into multiple stages.

Use the timing specifications to compute the propagation delay (t_PD).

The charging rate of the capacitor depends on the resistance in the circuit.

Use the timing specifications to compute the propagation delay (t_PD).