Consider a cache system with blocks of 2³ words, and words of 2³ bytes. Calculate the block number of the main memory for the address  598752 (decimal). Note: The anwer has to be provided in decimal (advise: convert 598752 to binary, work in binary and trasform the final solution from binary to decimal).

Consider a processor that generate the virtual address 0x00320F28 in the IF stage of a pipeline processor. Assuming that the corresponding instruction is in the cache memory (we have a cache hit), calculate the time (in number of cycles) required for performing the translation

from virtual  (VA) to physical (PA) address of the previous address, asuming that a hit on the TLB requires 0.25 cycles and a miss requires 27 clock cycles (TLB access is performed in parallel with page table access). Assume that we have pages of 4KB and the

state of the TLB and page table are:

Page Table           TLB

1 452 3A           

VA= Virtual Adress, PA= Physical Address, V= Valid bit

Consider a Virtual Memory System with virtual address of 48 bits and physical addresses of  28. The cache has the organization (2) (see below). The size of the cache is 2⁵ Kbytes, words of 2² bytes, blocks of 2³  words. Calculate mininum size of the virtual page (in Kbytes) if we want that the access cache can be carried out in parallel with the access TLB

Cache organization

(0)  Direct mapped

(1) 2-way set associative

(2) 4-way set associative

Consider a two level cache system, where the processor generates 2368 memory references. The number of misses at level L1 is 103 and the miss rate at level L2 is 6.2%. Calculate the global miss rate in % (provide 4 decimal at least).

Calculate the hit time at  L2 cache in a 1.8GHz. processor assuming that the global average memory access time is 8.55 cycles, the hit rate at L1 is 93.8%, the miss penalty at L2 is 110 cycles, the number of misses at L2 is 57 and the number of misses at L1 is 4392. Give the result in ns.