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Estructura de Computadores (2025-26, Grado en Ingeniería del Software. Plan 2023 Grupo B, Grado en Ingeniería Informática. Plan 2023 Grupo B y Grado en Matemáticas + Ingeniería Informática. Plan 2023 Grupo B)

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Calculate the physical address of main memory of a data of one byte wich is currently in cache memory, assuming a 2-way set associative organization. The data is the word 1 of a block in memory which is located in the set 23 of the cache. The cache has a size of 2⁶ Kbytes, blocks of 2⁴ bytes (consider words of 1 byte) and the assocciate TAG is 65 (decimal).

Note: provide the result in decimal

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Consider a cache with 16 bytes per block (words of 1 byte). Calculate the TAG for a direct mapped organization for the address 3883832 (decimal), assuming that the cache has 2⁷ blocks. Note: the solution have to be written in decimal (advise: transform the address to binary, work in binary and transform the final result to decimal). Note: for systems with word of 1 byte, the byte_offset field does not exist

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A processor with a main memory of 2¹ Mbytes has a cache memory of 2⁸Kbytes, and blocks of 2⁷ bytes (words of 1 byte). Assume a 4-way set associative organization. Calculate the size (number of bits) of the field "index" in an physical address.

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Consider a cache memory of 4 bytes per block (words of 1 byte). Calculate the TAG for a 2-way set associative organization for the address 576782 (decimal), assuming 2⁸ blocks in the cache. Note: the solution have to be written in decimal (advise: transform the address to binary, work in binary and transform the final result to decimal). Note: If the word is 1 byte, the byte_offset field does not exist.

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Consider a benchmark where 5% of the instructions are inconditional jumps, 8% are calling to routines, 10% are conditional branch (the branch condition is satisfied in 47% of the cases) and 3% are load instructions (lw) (33% of the loads are followed by an instruction with data dependency).

Consider two processors P0 and P1 both using the branch not taken predition technique. Nevertheless, for any jump (j, jal, beq & bne), the update of the PC in processor P0 is carried out in the memory stage whereas P1 updates the PC in the execution stage. The data hazards are solved by hardware (full forwarding).

Ignoring the initial transiet (4 cycles), calculate the CPI for the processor P0 (give the result with three decimal digits at least).

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Consider a benchmark where 5% of the instructions are inconditional jumps, 4% are calling to routines, 26% are conditional branch (the branch condition is satisfied in 78% of the cases) and 5% are load instructions (lw) (38% of the loads are followed by an instruction with data dependency).

Consider two processors P0 and P1 both using the branch not taken predition technique. The architecture of the processors uptade the PC as follow:

P0: j & jal, PC is updated in ID stage; conditional branches (beq & bne) in MEM stage

P1: j & jal, PC is uptated in IF stage*; conditional branches (beq & bne) in EX stage

The data hazards are solved by hardware (full forwarding).

Ignoring the initial transiet (4 cycles), calculate the CPI for the processor P1, (give the result with three decimal digits at least).

* This configuration is possible by using a (BTB)

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Consider a RISC-V architecture of 6 states IF, ID, EX1,EX2,M,WB where the new stage EX2 is due to the multiplication operation (mul). This operation takes two cycles. Thus, the adition/substraction/logical operations take one cycle (and calculate the result in the EX1 stage) whereas de multiplication calculte its result in EX2.

Calculate the execution time (in ns.) for the next code, assuming that the processor has a hazard unit to insert as many bubbles as required (no bypasses at all, including the RF). The cycle time is 19 ns.

or $25, $16,$19

Calculate the execution time (in ns.) for the next code, assuming that the processor has a hazard unit to insert as many bubbles (stalls) as required and there are forwarding in the RF (Register File) only (no bypasses in the rest of stages). The cycle time is 19 ns.

or $25, $14,$19

Calculate the execution time (in ns.) for the next code, assuming that the processor has full forwarding and it inserts bubble (stalls) in the pipeline when needed. The cycle time is 25 ns.

Calculate the execution time for the next code, assuming that the clock cycle is 8 ns., assuming that different registers hold different values (for example the content of $4 is different from the content of $8). Consider that your processor has the forwarding configuration number (1) (see the different configurations below).

add $10,$4,$29

sub $10,$0, $10

add $29,$29,$0

bne $0,$29,300

Forwarding configurations

(0) Full bypass

(1) Bypass between MEM-EXE only

(2) Forwarding inside the Register File only

(3) No bypass at all (only bubble insertion)

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