Consider a RISC-V architecture of 6 states IF, ID, EX1,EX2,M,WB where the new stage EX2 is due to the multiplication operation (mul). This operation takes two cycles. Thus, the adition/substraction/logical operations take one cycle (and calculate the result in the EX1 stage) whereas de multiplication calculte its result in EX2.

Calculate the execution time (in ns.) for the next code, assuming that the processor has a hazard unit to insert as many bubbles (stalls) as required and the next bypasses are available:

 EX1-EX1, EX2-EX1, M-EX1, RF (Register File). The cycle time is 19 ns.

or   x25, x12,x19

Consider a RISC-V architecture of 6 states IF, ID, EX1,EX2,M,WB where the new stage EX2 is due to the multiplication operation (mul). This operation takes two cycles. Thus, the adition/substraction/logical operations take one cycle (and calculate the result in the EX1 stage) whereas de multiplication calculte its result in EX2.

Calculate the execution time (in ns.) for the next code, assuming that the processor has the configuration (0) and a hazard unit to insert as many bubbles as required. The cycle time is 21 ns.

or   $25, $10,$21

CONFIGURATIONS:

(0) --> By pases EX1-EX1, EX2-EX1, M-EX1, RF (Regiter File)

(1) --> Only in RF

Calculate the total execution time in ns. for a pipelined RISC-V processor for the next code, assuming that the clock cycle is 14 ns. There is forwarding in the Register File only (the rest of data hazards are solved by bubble insertion).

or x12,x3,x5

sub x27,x10,x0

and x12,x0,x27

Calculate the execution time (in ns.) for the next code, assuming that the processor has the configuration (2) and a hazard unit to insert as many stalls (bubbles) as required. The cycle time is 14 ns.

sub x22, x10,x30

CONFIGURATIONS:

(0) --> Full bypass

(1) --> Bypases Mem-ALU and in the RF

(2) --> Bypass MEM-ALU only

Consider that the number of cycles for the execution of some instructions of a ISA is given by

add --> 6 cycles

xor  --> 2 cycles

lw   --> 2 cycles

sw   --> 4 cycles

multi --> 4 cycles

For the next code:

add $1,$2,$3

lw $4,100($2)

lw $5,100($3)

multi $6,$6,-1

xor  $1,$2,$3

add $8, $2,$13

sw $4,200($3)

sw $14,200($10)

add $11,$12,$13

lw $15,100($3)

Consider that the number of cycles for the execution of some instructions of a ISA is given by

add --> 5 cycles

xor  --> 2 cycles

lw   --> 2 cycles

sw   --> 5 cycles

multi --> 5 cycles

For the next code:

add $1,$2,$3

lw $4,100($2)

lw $5,100($3)

multi $6,$6,-1

xor  $1,$2,$3

add $8, $2,$13

sw $4,200($3)

sw $14,200($10)

add $11,$12,$13

lw $15,100($3)

The ISA of a processor has four types of instructions: arithmetic, store, load and  branch which require 1, 4, 3 and 2 cycles respectively. Assume a program composed by 553 arithmetic operations, 208 stores, 552 loads and 581 branches. What is the execution time of the program in a 1.9 GHz processor? Give the result in microseconds (μs). 

Find the number of instructions (NI) in the execution of a program which takes  94 μs. We know that  the average number of cycles per instruction (CPI) is 2.0 and that the processor works at  486 MHz (note: if a decimal value is obtained in the result, please write only the integer part; for example, if the solution is 3.6, you will write 3).

Find the average number of cycles per instruction (CPI) in the execution of a program which takes 6.6 μs to be executed, and taking into account that the number of executed instructions (instructions count) is 6171.6 with a processor working at  1214 MHz (give the solution with only one decimal).

Find the clock rate (in MHz) required for a processor taking into account that the execution of a program takes  2.5 μs, the number of cycles per instruction (CPI) is 4.0 and the instruction count (NI) is 501 (note: in case of having a decimal value, please write only the integer part; for example, it the solution is 4.7, you should write 4)