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ECE3161 Analogue Electronics - MUM S2 2025

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Q5. Find the small signal gain

Consider the common-base amplifier shown below, where the output resistance r_or_o of the NPN BJT is drawn explicitly. Estimate the small signal gain v_{out}/v_{in}v_{out}/v_{in} for this amplifier using the Miller's theorem. In your estimation assume r_or_o is large enough to allow the approximation v_{out}/v_{x} = g_m R_C v_{out}/v_{x} = g_m R_C when you apply Miller's theorem to simplify the circuit. 

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Q4. Find the input impedance of the circuit

The BJT transistor circuit below is shown with its parasitic capacitance C_{\pi}C_{\pi},  C_{\mu}C_{\mu} and  C_{\text{CS}}C_{\text{CS}}. Find the input impedance Z_{in}(s)Z_{in}(s) using Miller's theorem. Assume \beta\beta and g_mg_m given for this setup. Here ss is the Laplace variable. 

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Q3. Find the input resistance

For the ideal op-amp circuit given below, using Miller's theorem, find the input resistance R_{in}R_{in} as indicated?

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Q2. Find the output waveform

If the input to the op-amp circuit below is A\text{sin}(\omega t) + B\text{cos}(2 \omega t)A\text{sin}(\omega t) + B\text{cos}(2 \omega t) where AA and BB are constants, and \omega\omega is the angular frequency, what is the output waveform? Assume that the op-amp input impedance is infinite but it has a frequency dependent differential gain given by \frac{G\omega_0}{(\omega_0+j \omega)}\frac{G\omega_0}{(\omega_0+j \omega)} , where GG is a constant and \omega_0\omega_0 is a constant. 

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Q10. Find the input and output impedance

For the biased transistor below, find the input impedance Z_iZ_i, and the output impedance Z_oZ_o.

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Q9. Find the output impedance of the biased NMOS

For the biased NMOS transistor below, find the output impedance, Z_oZ_o. The NMOS has V_t=2V_t=2V, and it carries drain current of 50mA when V_{GS} = 5V_{GS} = 5V. Assume all three capacitors to be very large, so can be considered short circuited for signals. 

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Q8. Find the small signal gain 

For the biased transistor below, find the small signal gain v_o/v_iv_o/v_i. The JFET has I_{\text{DSS}} = 15 I_{\text{DSS}} = 15 mA and V_{\text{GS(off)}}=-3V_{\text{GS(off)}}=-3V. Assume all three capacitors to be very large, so can be considered short circuited for signals. 

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Q7. Find the small signal gain 

For the biased transistor below, find the small signal gain v_o/v_iv_o/v_i. Assume all three capacitors to be very large, so can be considered short circuited for signals. 

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Q6. Find the small signal gain 

For the biased transistor below, find the small signal gain v_o/v_iv_o/v_i. Assume all capacitors to be very large, so can be considered short circuited for signals. 

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Q5. Find the small signal gain 

For the biased transistor below, find the small signal gain v_o/v_iv_o/v_i. The NMOS has V_t = 0.8V_t = 0.8V and  V_A = 20 V_A = 20V. Assume all three capacitors to be very large, so can be considered short circuited for signals. 

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