Consider the MIPS instruction SW $t1, -4($sp). What is the effective address if $sp = 0x7FFFFFFC?

A MIPS instruction LB $t0, 3($s2) is executed. What happens if the memory location contains 0xFF?

In MIPS, a J (jump) instruction has a 26-bit address field. If the current PC is at 0x00400000, what is the maximum jump target address?

A MIPS processor uses a 16-bit immediate field for an I-type instruction. If an immediate value of 0xF534 is used in an ADDI instruction, what will happen?

In MIPS, which of the following instructions correctly loads a word from memory using base addressing mode if register $s1 holds the base address?

A branch instruction is predicted incorrectly in a 5-stage pipeline with one cycle branch resolution delay. How many cycles are wasted per misprediction?

Consider a branch instruction with the following execution statistics:

• 40% taken branches

• 60% not taken branches

• A static branch predictor always assumes ‘not taken’

What is the branch prediction accuracy?

A) 40%

A processor uses delayed branching and executes a branch instruction at cycle 5. If the delay slot is filled with an instruction that takes 3 cycles, what happens?

In a superscalar pipeline, how does a mispredicted branch impact instruction execution?

A processor uses a dynamic two-bit branch predictor. If a branch instruction is initially mispredicted twice but correctly predicted three times in a row, what will be the final state of the predictor?