A 32-bit processor performs a circular left rotation (ROL) on register R1 = 0xC3A5F4B7 by 8 bits. What is the new value of R1?

A CPU supports a NOR instruction that performs NOT(A OR B). If A = 0b11001100 and B = 0b10101010, what will be the result of A NOR B?

Consider a 64-bit system where logical operations are performed in parallel on 8-bit sections (SIMD). If AND operation is performed between:

• R1 = 0xFF00FF00FF00FF00

• R2 = 0x0F0F0F0F0F0F0F0F

What will be the result stored in R3 = R1 AND R2?

 A CPU uses a barrel shifter to perform logical shifts. If a 16-bit value R1 = 0b1011001100110011 is right-shifted logically by 4 positions, what is the new value?

A 32-bit processor performs a bitwise XOR operation between two registers: R1 = 0xF0F0F0F0 and R2 = 0x0F0F0F0F. What will be the result stored in R3 = R1 XOR R2?

A) 0xFFFFFFFF

In an ISA, an instruction supports indirect addressing mode. What happens when an instruction like LOAD R1, (R2) is executed?

A system uses variable-length instructions with a base instruction size of 16 bits and extensions of 8 bits each. If an instruction requires two additional operands and a displacement value, what is the total instruction length?

 A CPU uses a 16-bit instruction format with the following breakdown:

• 4 bits for the opcode

• 3 bits for the first operand

• 3 bits for the second operand

• 6 bits for an immediate value

What is the maximum number of distinct instructions the CPU can support?

In a load-store architecture, which of the following statements is true about instruction execution?

A processor uses a three-address instruction format. If an operation like ADD R1, R2, R3 is executed, how many memory accesses are required, assuming a register-memory architecture with no cache?