A computer system has a pipelined execution model where the probability of a stall due to a data hazard is 15%, and the average stall penalty is 2 cycles. If the ideal CPI is 1, what is the actual CPI considering data hazards?

Consider a superscalar processor capable of issuing 4 instructions per cycle. If a program has 1000 instructions and executes with an average Instruction-Level Parallelism (ILP) of 2.5, how many cycles will it take to complete execution (ignoring stalls and dependencies)?

A processor has a cache hit rate of 80% and a cache access time of 2 cycles. If the main memory access time is 50 cycles, what is the average memory access time (AMAT)?

A CPU has separate functional units for integer and floating-point operations. An instruction mix contains 40% integer operations, 30% floating-point, and 30% memory operations. If the integer unit completes an operation in 1 cycle, the floating-point unit in 3 cycles, and memory operations in 2 cycles, what is the average cycles per instruction (CPI)?

A processor has a 5-stage pipeline (Fetch, Decode, Execute, Memory, Write-back). If a branch instruction is encountered and mispredicted 25% of the time, with a 2-cycle penalty per misprediction, what percentage of total cycles is wasted due to branch mispredictions if 10% of all instructions are branches?

In a deeply pipelined processor, which factor has the MOST significant impact on performance degradation due to branch instructions?

Consider a system where the memory unit implements a Harvard architecture. Which of the following would be an advantage of this approach?

Which of the following best describes the role of the Reorder Buffer (ROB) in out-of-order execution?

In modern CPUs, the register renaming technique is primarily used to:

1. In a superscalar processor, how do multiple functional units contribute to instruction execution?