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Course 86819
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Consider a 2-input dynamic NAND gate with VDD = 2 V, Vtn = 0.5 V = - Vtp, K’n = 3 K’p = 300E-6 A/V2 W/L = 1.5 for all QN, W/L =3 for all QP, and CL = 10 fF (completely Discharged). During Precharge: Calculate ID at Vout = VY = 0.1 VDD. If ID = 82.5E-6 A at Vout = VY = 0.9 VDD, Calculate the rise time tr.
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Consider a 2-input dynamic NAND gate with VDD = 2 V, Vtn = 0.5 V = - Vtp, K’n = 3 K’p = 300E-6 A/V2 W/L = 1.5 for all QN, W/L =3 for all QP, and CL = 10 fF. During Evaluation: Calculate ID at Vout = VY = VDD (starting of discharge of CL). If ID = 101.25E-6 A at Vout = VY = VDD/2, Calculate tPLH.
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Find VDsat for an NMOS transistor fabricated in 0.4E-6 m technology with electron mobility of 400 cm2/V.S
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A CMOS Transmission Gate (TG) is Constructed from An NMOS transistor in Parallel to PMOS Transistor:
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Velocity Saturation in deep submicron technology will cause ID in PMOS and ID in NMOS to:
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Consider the Circuit in Figure E15.17 in the formula sheet to generate the reference voltage VR. Assume VD1 = VD2 = VBE = 0.7 V, and IB of Q1 = 0 A. Calculate ID1 = ID2, VB of Q1, and VR.
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Find the approximate value of tPLH for a CMOS transmission gate if (W/L) = 1.0 for NMOS and PMOS. Knowing that CL = 70 fF.
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Suppose that in the scaling table 15.1, VDD and Vt remain constant. If the scaling factor is 1/S, Then Pdyn is scaled by:
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For the basic ECL gate in the formula sheet: Let VCC =2 V, I4 = 4mA, and RC = 500 ohm. Determine VOL, VOH, and VR to be centered between VOL and VOH
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A CMOS Transmission Gate (TG) is Constructed from An NMOS transistor in Series to PMOS Transistor:
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