The decreasing feature size complicates verification

Salaries are going up

The number of logic gates is increasing

CAD tool costs are going up

Back-annotated timing

Signal integrity verification

RTL simulation

Logic sythesis

Standard Cell ASIC

Gate Array

FPGA

Salaries are going up rapidly

The number of logic gates increases with each node

The smaller feature sizes complicate verification

CAD tool costs are going up rapidly

An RTL input for a design

A layout for mask making

A set of logic gates and how they are connected

Timing specification for the design

F = A’BD + AB

F = ABC

F = AC

F = BD

Minimizing the need for long distance interconnect.

Mazimizing the amount of the design captured as software in the emebdedd cores.

Using the specialized IO as much as possible.

Maximizing the ratio of flip-flops to logic.

Programing the clock so as to enable clock gating.

Trying to make the clock as fast as possible.

Adding interconnect-heavy features to your design to take advantage of the programmable switch matrices.

Tailoring your design to take advantage of the specific logic structures offered in an FPGA.

A module whose only performance requirement is to operate at the minimum possible power level.

A module which must sometimes perform at high performance but at other times does not need to be on at all.

A module whose performance goal is to minimize power.delay product.

A module which must sometimes perform at high performance but at other times needs to perform at a low performance.