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ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog

ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog

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Which of the following is true about semiconductor memories? Selecting incorrect answers will lead to a loss in points.

In a DRAM, the row and column addresses are sent separately on a single shared address bus.

✅

SRAMs support burst mode reads.

An attached SRAM can be read from inside the DUT with a statement like

always@(posedge clock) data<=Memory[Address]

❌

A random access to a new read address is faster in an SRAM than a DRAM.

✅

After reading from a first address in a DRAM, the content of the next address can be read faster than the content of the first address if it's in the same row.

✅

Non-volatile memories, such as flash, are generally slower than SRAM and DRAM.

✅

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What combination of properties describe assertions as used during the verification process?

Choose all that apply. Wrong answers will deduct points. Two are true.

They are only put in the testbench

❌

They are generally not synthesized.

✅

They constantly monitor the design for expected properties.

✅

They are only used to debug the design post-silicon.

❌

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When do you use compile – incremental in a synthesis run? Choose one.

All compiles after the first.

✅

All compiles.

❌

All compiles after minor changes in the RTL

❌

Compiles only when design rules are being asserted.

❌

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Which of the following are true about FPGAs? Two are true. Points are taken off for incorrect answers.

FPGAs allow fast product changes

✅

When fixed resources are available (e.g. specific sized multipliers) it is a good idea to write your code to explicitly use them.

✅

They can achieve equivalent clock rates as standard cell ASICs in the same fabrication technology (or node)

❌

It is the lowest cost solution when considering high volume production.

❌

They have enough wiring resources that this factor is not a design consideration.

❌

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Consider the following non-blocking assignments. Which choice gives the same logic?

always@(posedge clock)
  begin
    A <= in;
    B <= A;
    C <= in;
  end

None of these

❌

always@(posedge clock)
  begin
     C=in;  
     A=in;
     B=A;
  end

❌

always@(posedge clock)
  begin
    A=in;
    C=in;
    B=C;
  end

❌

always@(posedge clock)
  begin
    C=in;
    B=A;     
    A=in;
  end

✅

All of these

❌

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The

asynchronous FIFO still uses two receive flops in each direction on rptr and

wptr. Why does this not cause problems?

don’t care if we miss edges on these.

✅

The clocks are slow enough that we wont miss edges.

❌

Strictly speaking we don’t need these synchronizing

flops.

❌

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When

using an asynchronous FIFO, why is a gray code count sequence used when

communicating the FIFO pointer address between the clock domains

A gray code count is not strictly needed. The synchronizer will work without it.

❌

that the read and write pointers can be compared.

❌

that the count value never goes through “glitchy” non-sequential values that

might be accidently sampled.

✅

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