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ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog
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One way to employ a BIST strategy for logic is as follows:
Which of the following is most true as it applies to design for test (DFT):
What changes occur in the test sequence when doing delay fault testing?
What advantage does SystemVerilog have over Verilog 2001 when it comes to writing assertions?
When testing memories, it is important to:
If the following logic is built exactly as described, indicate a test vector that sensitizes a stuck-at-1 fault at g and propagates it to the output h. If the value of a particular input does not matter, indicate it as ‘x’ – don’t care.
wire a, b, c, d, e, f, g, h;
assign f = a ? b : c;assign g = d ^ f;assign h = e & g;
If your goal was to maximize performance per unit area, which FPGA design maximizes this metric? Assume a LUT takes four times more area than a register.
What best describes the reason for the need of the command uniquify -cell U3 -new_name bar2 in a synopsys script?
Continue the shift example started with
assign d0 = SC[0] ? {a[31],a} >> 1 : a; assign d1=SC[1] ? {{2{a[31]}},d0} >> 2 : d0;
What is the next stage of the shifter design?
Which of these determine what should be placed within one module? There is more than one selection that applies.