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ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog
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You are having difficulty meeting setup timing. What are some of the viable options available to you?More than one option might be viable. Wrong choices will deduct points.
You want to add four numbers together. Which logic is going to give the highest throughput and correct operation? Rank order the logic from the fastest throughput to the slowest. i.e. Which will give the fastest clock?
Option 1.
always@(posedge clock)
begin
A <= B+C;
E <= D+F;
G <= A+E;
end
Option 2.
always@(posedge clock)
begin
G <= A + E;
end
assign A = B+C;
assign E = D+F;
Option 3
always@(posedge clock)
begin
G <= B+C+D+F;
end
Option 4
always@(posedge clock)
begin
A <= B+C;
G <= (D+F)+A;
end
Consider the following code
reg [3:0] C;
assign C = {{2{B[0]}},B[B[2:1]},B[1]?B[0]:B[2]};
If B=4'b0110 what is the value of C? Give your answer in binary in big endian order. Don't include 4'b
What does the the following for loop build?
integer i;
reg A;
reg [3:0] B;
reg [7:0] C;
always@(*)
begin
A=1;
for (i=0; i<=B; i=i+1) if (C[B]) A = ~A;
end
In the standard class synthesis script, which of the following are specified in the synopsys setup file that must be in the same directory. More than one answer applies. Incorrect answers might lose points.
Consider the following non-blocking assignment. Which blocking alternative will give the same logic?
reg A, B, C, D;
always@(posedge clock)
begin
A <= D;
B <= C;
C <= B;
D <= A;
end
You are designing a new smart home thermostat that is powered by a small battery. You are unsure about the market size but expect to sell around 100,000 units of the first version. You are working with a design company that can design an ASIC, and FPGA or a gate array for you, and you have the budget to support any of these. Which would you pick?
Consider the following code implemented exactly as described.
module (input clock, start; output reg A, B, C, D);
always@(posedge clock)
begin
if (start) {A,B,C,D} = 4'hA;
else
begin
A <= (A & B) | (C & D);
B <= B ^ C;
C <= A ^ D;
D <= A ^ C;
end
end
Each logic gate has a delay of (1:2:6) (min:typ:max). If the clock period is 20 ns, and clock uncertainty is 1 ns, then what is the input delay that has to be used in another module that is connected to the outputs of this module. Give your answer as an integer without "ns”.
Consider the following code implemented exactly as described.
reg A, B, C, D;
always@(posedge clock)
begin
A <= (A & B) | (C & D);
B <= B ^ C;
C <= A ^ D;
D <= A ^ C;
end
Each logic gate has a delay of (1:2:4) (min:typ:max).
If the clock period is 20 ns, and clock uncertainty is 1 ns, then what is the excess slack in this design. i.e. By how many ns could you reduce the clock and still meet timing. Give your answer as an integer answer without units.