None of the above are valid uses

To reduce the amount of coding for repeated logic and can include timing statements

To reduce the amount of coding for repeated combinational logic, but no timing

To make it simpler to build repeated modules

Can be used in place of a module call

out = 4’b0111;

out = 4’b1000;

None of the answers.

out = 4’b0000;

out = 4’b0011;

Clock period, uncertainty; input clock-Q delay; input driver gate and pin; output setup delay; output load gate and pin

Area desired

Clock period, uncertainty; clock period lost to external delays to input pins;  input driver gate and pin; clock period lost to external delays from output pins; output load gate and pin

Clock period, uncertainty; Library choice; hold time repair rules

A right shift unit

An arithmetic left shift unit.

A left rotate unit (shift with wrap around)

A logical left shift unit.

To prevent hold violations.

Minimize the clock period.

Achieve a perfectly optimal design while trying to meet timing

Achieve a reasonably minimal area design while meeting realistic timing constraints.

During compile we use the slow version of the cell library to ensure that all chips will meet setup constraints.

During compile we use the fast version of the cell library so as to permit the maximum clock speed.

During compile we use the typical version of the cell library so we can meet setup constraints with a typical clock.

During compile we use the fast version of the cell library to ensure that all chips will meet setup constraints.

foo must be of type wire

Nothing is wrong

Counter must be instanced as u1

clock, in, latch and dec cannot take on the same names as the ports