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ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog
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After executing the following code, what is the value of f002 in U0.
module top();
parameter Gfoo = 2**3;
foobar #(.foo2(Gfoo)) U0 (.clock(clock));
endmodule
module foobar (.clock(clock));
parameter foo1=4;
parameter foo2=16;
…
endmodule
What is the function of the reset signal?
Your reference algorithmic C code uses a for loop. What might you consider for implementing that part of the control strategy. Multiple answers might apply.
Consider the following code fragment intended for synthesis.
module top (input reset, clock, start; …)// start indicates a new frame of data, about once every ms
…
always@(start) begin reset=reset & 1’b0; #100 reset = reset & 1’b1; end
leafmodule u1 (reset, clock, …);leafmodule u2 (reset, clock, …);
endmodule
What is wrong with this code fragment. There are SEVERAL things wrong.
Consider the following FSD:
Which code fragment best matches the FSD?
Which are the two (out of three) "acceptable" state vector declarations for the above example? TWO correct answers are expected.
Which state encoding style is significantly faster than the others?
Which state encoding style generally leads to the smallest FSMs?