Crowdly

A layout for mask making

A set of logic gates and how they are connected

Timing specification for the design

(Note: the next question asks for the second most important reason)

What is the MAIN reason that design costs are increasing rapidly with succeeding fab nodes?

Salaries are going up rapidly

The number of logic gates increases with each node

The smaller feature sizes complicate verification

CAD tool costs are going up rapidly

Which implementation style would you choose for a 3D Ultra-HD video CODEC for a new camcorder line? These CODECs have to achieve high performance, especially for encoding video information at low power consumption. The standards it supports are fixed and the volume is large

Standard Cell ASIC

Gate Array

FPGA

The netlist is produced as one output from which tool?

Back-annotated timing

Signal integrity verification

RTL simulation

Logic sythesis

Why is it desirable to back-annotate information back from the layout in order to do accurate timing verification.

The standard cell designs can be changed by place and route.

Gate delay calculations require the gate layout.

Interconnect delay is best calculated from the actual layout

What logic function is equivalent to the following truth table (A’ means inverse of A).

F = A’BD + AB

F = ABC

F = AC

F = BD

In[] is applied to the D inputs of the flip-flops on the left, Out is the Q outputs of the flip-flops on the right. Specify the missing valies of out as 3 hex characters, without spaces, e.g. 010

Out of the following, the most important key to achieving a high equivalent logic gate count in an FPGA includes the following.

Minimizing the need for long distance interconnect.

Mazimizing the amount of the design captured as software in the emebdedd cores.

Using the specialized IO as much as possible.

Maximizing the ratio of flip-flops to logic.

Out of the following, the most important key to achieving a high equivalent logic gate count in an FPGA includes the following:

Programing the clock so as to enable clock gating.

Trying to make the clock as fast as possible.

Adding interconnect-heavy features to your design to take advantage of the programmable switch matrices.

Tailoring your design to take advantage of the specific logic structures offered in an FPGA.

Which of the following is a valid application demanding near-double-threshold voltage supply (typically 0.6 – 0.8 V)?

A module whose only performance requirement is to operate at the minimum possible power level.

A module which must sometimes perform at high performance but at other times does not need to be on at all.

A module whose performance goal is to minimize power.delay product.

A module which must sometimes perform at high performance but at other times needs to perform at a low performance.