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ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog

ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog

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A configurable logic block (CLB) slice generally includes the following:

Combinational logic built as lookup tables; steering logic and flip-flops/latches

Combinational logic built as lookup tables, programmable clocks, and flip-flops. Latches.

Combinational logic built as lookup tables, 18-bit adders and flip-flops/latches.

Combinational logic built as lookup tables, programmable switch matrix and flip-flops/latches.

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You are working out the design for a unit completing a a complex task. You have a choice of two algorithms. One requires 1000 multiply accumulates with 2000 caches reads. The other requires 2000 multiply accumulates with 1000 cache reads. Which would you choose to minimize energy per task?

2000 MACs and 1000 cache reads.

Both consume the same energy for the task.

1000 MACs and 2000 cache reads.

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IN a Xilinx Virtex 5, the difference between an M and a D slice is…

SRAM is only used in a M slice.

In an M slice, the embedded SRAMs can be used either as logic or as small memories.

The M slice containts the SRAMs only.

The M slice is smaller in area than the D slice.

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If “enable” is high 20% of the time , and the code below is synthesized, which of the following will have the absolutely lowest power consumption.

wire [31:0] A, B, D;

reg [31:0] E, F, G;

always@(posedge clock)

if (enable) E <= A * B;

else E <= 0 * 0;

wire [31:0] A, B, D, MultIn1, MultIn2, MultOut;

reg [31:0] E, F, G;

always@(posedge clock)

MultIn1 = enable ? A : 0;

MultIn2 = enable ? B : 0;

E = MultIn1 * MultIn2;

wire [31:0] A, B, D;

reg [31:0] E, F, G;

always@(posedge clock)

if (enable) E <= A * B;

wire [31:0] A, B, D;

reg [31:0] E, F, G;

always@(posedge clock)

assign AA = enable ? A : 0;

assign BB = enable ? B : 0;

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Which of the following is a valid application in which sleep transistors are likely to be useful.

A module whose only performance requirement is to operate at the minimum possible power level.

A module which must sometimes perform at high performance but at other times does not need to be on at all.

A module whose performance goal is to minimize power.delay product.

A module which must sometimes perform at high performance but at other times needs to perform at a low performance.

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Which of the following is a valid application of Clock Gating?

A module whose only performance requirement is to operate at the minimum possible power level.

A module which must sometimes perform at high performance but at other times does not need to be on at all.

A module whose performance goal is to minimize power.delay product.

A module which must sometimes perform at high performance but at other times needs to perform at a low performance.

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Which of the following is a valid application of Dynamic Voltage and Frequency Scaling?

A module whose only performance requirement is to operate at the minimum possible power level.

A module which must sometimes perform at high performance but at other times does not need to be on at all.

A module whose performance goal is to minimize power.delay product.

A module which must sometimes perform at high performance but at other times needs to perform at a low performance.

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In the notes, energy was computed using the following equation.

Energy = S _cycles S _nodes N_switch f Vdd² C_load+ leakage power * time

S represents the symbol for a Summation

The energy consumed in dynamic switching could be rewritten as.

S_nodes N_switch Vdd² C_load

Where N_switch is the percentage of clock cycles the node completes a 010 or 101 transition during its operation.

S_nodes N_total Vdd² C_load

Where N_total is the total times the node completes a 01 or 10 transition during its operatio

S_nodes N_total Vdd² C_load

Where N_total is the total times the node completes a 010 or 101 transition during its operation.

leakage power * time captures the dynamic power.

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Which of the following is a valid application demanding sub-threshold voltage supply?

A module whose only performance requirement is to operate at the minimum possible power level.

A module which must sometimes perform at high performance but at other times does not need to be on at all.

A module whose performance goal is to minimize power.delay product.

A module which must sometimes perform at high performance but at other times needs to perform at a low performance.

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Which of the following is most true as it applies to design for test (DFT):

Scan-path testing is used to give access to the internal combinational logic from the chip I/O.

Design of a good DFT strategy is critical to helping you debug the chip before sending it to fabrication.

Random testing is always preferable to scan path testing.

Running your verification vectors on your chip to test it will ensure that there are no manufacturing defects in the chip.

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