When

going from a slow domain to a fast clock domain, which clock crossing technique

is needed?

Which of the following statements are true about clock domain crossing?  Two are true.  Incorrect selections lose points.

If  “enable” is high only 10% of the time, and the code below is synthesized, which of the following will have the lowest power consumption.  Don’t forget about resource sharing and optimization in synthesis.

If  “enable” is high 20% of the time , and the code below is synthesized, which of the following will have the absolutely lowest power consumption.   

Which of the following MAC designs will achieve the

desired computation for the least total energy per useful computation on

average?  To help you in your

considerations, you can use the following data.   The average energy consumed in a cycle when

any of the inputs change are as follows:

Multiplier 50 pJ

Adder 20 pJ

Register 10 pJ

Mux 5 pJ

Note enable’s typical behavior is to go high for over 90%

of the time.  A and B change on all clock

cycles.

Each logic is implemented exactly as described.  The compiler performs no optimizations.

Choose one option.  Note the choice

button might be ABOVE the matching text. 

Don’t accidently choose the button below.

In the notes, energy was computed using the following equation.

Energy = S _cycles S _nodes N_switch  Vdd² C_load + leakage power * time

S represents the symbol for a Summation

The energy consumed in dynamic switching could be rewritten as.

Consider the following alternatives implemented exactly as described.  K is zero for roughly every other cycle.  Which has the lowest power consumption?  K and In are 32-bits wide.

The clock periods are the same.  

In the clock domain crossing FIFO design, why are their

two registers on wptr and rptr pins controlled by the other domain’s

clock?  Choose one answer.