Consider the following code fragment.  Notice the use of non-blocking assignment.

always@(posedge clock)

begin

  B <= A^C;

  C <= B;

end

Which BLOCKING code version would lead to identical logic (after any potential logic gate sharing is taken into account)?

The code fragment is likely to implement unintended latches?

always@(posedge clock)

state <= next_state;

always@(state or A)

begin

  out = 0;

  case (state)

    0 : if (A) begin

                 out = 1;

                 next_state = S0;

               end

        else next_state = S1;

     1 : next_state = S0;

  end

Is the following code fragment, that of a Mealy or Moore machine?

always@(posedge clock)

state <= next_state;

always@(state or A)

begin

  out = 0;

  case (state)

    0 : if (A) begin

                 out = 1;

                 next_state = S0;

               end

        else next_state = S1;

     1 : next_state = S0;

  end

Assuming the code in the question above is synthesizable, what is the code doing?

Is this a valid, synthesizable, use of a for loop?

reg [8:0] A, B;

integer i;

parameter N=8;

always@(B)

begin

  for (i=1; i<=N; i=i+1)

    A[i-1]=B[i];

  A[N] = A[N-1];

end

You have to build a part that has numerous 256 Mbps inputs and you are required to perform real time processing on them.  The volume is high. Which implementation style would you choose?

What are the TWO things wrong with the following code fragment?

always@(A orB or C)

  begin

    F = A & C;

    A = F | B;

end

      always@(B or D)

begin

    F = D ^ B;

  end

Would you expect to achieve a 1 GHz clock with an FPGA?

What is wrong with the following code fragment (note the use of non-blocking assignment)?

always@(A or B or C)

  begin

    E <= C | B;

    F <= E ^ A;

  end

What is wrong with the following code fragment?

always@(A or C)

    D = A & C;

always@(posedge clock)

     if (B) E <= C;