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ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog
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Which figure below best represents the logic being modeled in the following Verilog code?
always@(posedge clock)
begin
A<= D|C;
A<= B^C;
A<= E&F;
end
Which of the two codes generate the same logic?
(A) input [2:0] A;
input F;
reg [1:0] Y;
always@(A or F)
begin
if (A[2]) Y = 2’b11;
else if (A[1]) Y = {1’b0,F};
else if (A[0]) Y = {F,1’b0};
else Y = 2’b00;
end
(B) begin
casex (A) //synopsys full_case
3’b1xx : Y = 2’b11;
3’b01x : Y = {1’b0,F};
3’b001 : Y = {F,1’b0};
default : Y = 2’b00;
endcase
end
(C) input [2:0] A;
input F;
reg [1:0] Y;
always@(A or F)
case (A) \\ synopsys full_case parallel_case
3’b100 : Y = 2’b11;
3’b010 : Y = {1’b0,F};
3’b001 : Y = {F,1’b0};
default : Y = 2’b00;
endcase
Of what type must A be declared?
XOR u1 (B, C, A); // A is the output
Consider the following code fragment (note the use of non-blocking assignment)?
always@(posedge clock) begin A <= B; B <= C; end
Would the described function change if blocking assignment was used instead?
Of what type must A be declared?
assign A = B^C;
Of what type must A be declared?
always@(*) A = B^C;
Choose the correct verilog code to describe the following diagram
What logic function does the following code fragment describe?
always@(posedge clock) begin for (i=8; i>=1; i=i-1) A[i] = A[i-1]; A[0] = In; end
What is wrong with the following code fragment?
always@(A or B or C) begin F = A & C; A = F | B; F = F ^ B; end
What is wrong with the following code fragment?
always@(A or B or C) begin if (C) E = C | B; end