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ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog
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What is wrong with the following code fragment intended for synthesis?
reg foo;counter u2 (.clock(clock), .in(in), .latch(latch), .dec(dec), .zero(foo)); // counter is from the notes
Consider the following code (implemented exactly as described):
reg A, B, C;always@(posedge clock) A <= B;always@(posedge clock)
B <= (A | C) & B;always@(posedge clock)
C <= A;The minimum and maximum delays between each set of successive gates are marked as #(min: typical: max) ns and are marked on the output node of the driving gate. (Remember the timing equations are ≤ and ≥ constraints). You also need the following:
- T_setup = #(1 : 1 : 2) ns.
- T_hold = #(1: 1 :2) ns.
- T_skew = #(1: 1 : 1) ns for the clock.
- T_clock-Q = #(2 : 3 : 5) ns.
- T_logic = #(1 : 2 : 3) ns for each and every logic gate from any input to any output.
What is the fastest possible clock period that satisfies setup constraints across all variations? Give the answer in ns without the units
What is wrong with the following code fragment intended for synthesis?
wire foo;always@(*)foo = A | B;In the following test fixture, what is the timing diagram being specified?
initialbegindec = 0; run = 0; ck = 1;#10 dec =1; run = 1;#10 run = 0;#20 $finish;endalways #5 ck = ~ck;In general, the designer can choose whether the clock skew is positive or negative between any pair of flip-flops.
Consider the following code (implemented exactly as described):
reg A, B, C;always@(posedge clock) A <= B;always@(posedge clock)
B <= (A | C) & B;always@(posedge clock)
C <= A;The minimum and maximum delays between each set of successive gates are marked as #(min: typical: max) ns and are marked on the output node of the driving gate. (Remember the timing equations are ≤ and ≥ constraints). You also need the following:
- T_setup = #(1 : 1 : 2) ns.
- T_hold = #(1: 1 :2) ns.
- T_skew = #(1: 1 : 1) ns for the clock.
- T_clock-Q = #(2 : 3 : 5) ns.
- T_logic = #(1 : 2 : 3) ns for each and every logic gate from any input to any output.
Is there potential for a hold violation? T/F
What is wrong with the following code fragment intended for synthesis?
reg[3:0] A;initialA =’4’b000 1;always@(posedge clock)A <= C;Is there potential for a hold violation in the schematic above?
Consider the 3-level clock tree shown. If the 6-sigma variation in clock buffer delay is +/- 20 ps, and the post-routed delay of each buffer-to-buffer or buffer-flip-flop wire can vary by +/- 5 ps from the pre-layout delay estimate, what is the expected clock skew? Assume you can just add the 6-sigma variation to get the final variation.Give your answer as a number (in ps). For example, if the answer is 25 ps, just enter 25
The details of the logic design have a strong impact on achievable clock speed