What does the following line of Verilog code do? 

\\ synopsys off

Both of these questions apply to the following code implemented exactly as described.

module A1 (input clock, E, F; output reg A, B);

wire C

always@(posedge clock)

   begin

    A <= C;

    B <= F;

   end

assign C = E | F;

endmodule

Each gate has a delay from its input to output as given as {1 : 2 : 3}, t_Cp_Q is {2 : 3 : 5} the clock skew is 1 ns, the flip-flop setup time is 1 ns and the hold time 1 ns.  Format above is {min : typical : max}. 

This module is part of a hierarchy 

     A1 U1 (clock, E, F, A, B);

     A2 U2 (clock, A, B, E, F);

A2 is another module with a clock two inputs and two outputs.  If you were synthesizing A2 by itself, (i.e. A1 is not being synthesized in the same run) what vales should be assigned for input delay and output delay for the ports of module A2.  Ignore any interconnect delay.

 Give your answers as integers

 Inputs delay

Consider the following code fragment:

     U1 thingy (clock, A, B);

     U2 thingy (clock, C, D);

The interfacing logic connected to A and B has very different timing than the interfacing logic connected to C and D.  Choose a short script fragment that ensures this will synthesize correctly including the actual compile(s). 

What style is the following FSM code fragment?

always@(posedge clock) state <= next_state;

always@(state or A)

begin

  casex (state)

     2’b01 : if (A) next_state = 2’b10;

             else next_state = 2’b01;

     2’b10 : next_state = 2’b01;

     2’bxx : next_state = 2’b01;

  endcase

assign out = |next_state;

Choose the logic being described by the following statement group.  .  In XOR(A,B,C) B and C are inputs, A is an output

wire [3:0] A, B, C;

 assign C = {4{B[3]},B} >> 2;

You are designing a security chip for use in a high volume battery-driven application.  Special logic structures are required in order to make the chip secure against reverse engineering its logic details.  What design style are you like to use? 

The main purpose of adding Design For Test (DFT) features is to help debug the chips as they come off the factory floor? 

The code fragment below is likely to implement unintended latches?

always@(posedge clock) state <= next_state;

always@(state or A)

begin

  casex (state)

     2’b01 : if (A) next_state = 2’b10;

             else next_state = 2’b01;

     2’b10 : next_state = 2’b01;

     2’bxx : next_state = 2’b01;

  endcase

assign out = |next_state;

What does the following primitive describe:

primitive PlanetX (A, B, F);

output F;

reg F;

input A, B;

table

0 0 : 0

0 1 : 1

1 1 : 0

1 0 : 1

endtable

endprimitive

If the following logic is built exactly as described, derive a test vector sensitizes a stuck-at-1 fault at c and propagates it to the output h.

wire a, b, c, d, e, f, g, h;

assign f = a ? b : c;

assign g = d | f;

assign h = e & g;