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ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog
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The main purpose of adding Design For Test (DFT) features is to help debug the chips as they come off the factory floor?
The code fragment below is likely to implement unintended latches?
always@(posedge clock) state <= next_state;
always@(state or A)
begin
casex (state)
2’b01 : if (A) next_state = 2’b10;
else next_state = 2’b01;
2’b10 : next_state = 2’b01;
2’bxx : next_state = 2’b01;
endcase
assign out = |next_state;
If “enable” is high around 30% of the time, and the code below is synthesized, which of the following will have the lowest power consumption.
Choose the logic described by the following code fragment. Note the use of blocking assignment. All variables are one bit wide.
always@(posedge clock)
begin
C = A | B;
E = C & D;
D = C ^ A;
end
What is wrong with the following code fragment?
always@(*)
begin
A = E ^ D;
if (C) E = ~A;
else E = D;
end
What logic function does the following code fragment describe? Choose the logic netlist that captures the design AS DESCRIBED (NOT MINIMIZED). All variables are 1 bit wide. In XOR(A,B,C) B and C are inputs, A is an output
always@(*)
begin
A = B ^ D;
if (E) A = A | E;
else A = A ^ E;
end
What logic function does the following code fragment describe. Chose the correct netlist. A is 4 bits wide. Sketch the logic AS DESCRIBED (NOT MINIMIZED). . In XOR(A,B,C) B and C are inputs, A is an output
integer i;
always@(*)
begin
N = 0;
for (i=0; i<=3; i=i+1)
N = N | A[i];
end
What is wrong with the following code fragment?
always@(posedge clock)
begin
D <= A & C;
if (E) G <= D | F;
end
Consider the logic described by the following code fragment. Note the use of blocking assignment. All variables are one bit wide. There might be more than one correct answer. Note, selecting incorrect answers will result in the loss of points.
always@(posedge clock)
begin
C = A | B;
E = C & D;
D = C ^ A;
end
Which code fragment produces identical logic? (May have more than one correct answer)
Consider the logic described by
wire [3:0] A, B, C;
assign C = {4{B[3]},B} >> 2;
If B was initially 4’b1010, what is it after the assignment? Give your answer as just bits without any 4’b, e.g. 0011