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CA & OS (Computer Architecture) - EFREI - Fall 2026

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Risque de guerre

This type of hazard may occur when the latter instruction (j) stores the result of its execution in the resource (register or memory location) that earlier instruction (i) uses as their argument. The problem appears when the execution of earlier instruction (i) is delayed, and the latter instruction (j) is finished before earlier instruction (i) can take its argument. It may lead to a  wrong result of the execution instruction (i). The typical way to remove such a dependency is to delay the completion of the execution instruction (j) until the execution of instruction (i) is completed. 

To illustrate this problem, the following code will be used:

;WinMIPS64 WAR hazard example

    .data

A:    .double 10.0

B:    .double 5.0

C:    .double 3.5

D:    .double 1.0

E:    .double 3.14.0

res:    .double 0.0

    

    .text

main:    

    LDC1 f2,A(r0)

    LDC1 f3,B(r0)

    LDC1 f4,C(r0)

    LDC1 f5,D(r0)

    LDC1 f6,E(r0)

    

    add.d f2,f2,f3

    sub.d f2,f2,f4

    mul.d f4,f5,f6

    

    SDC1 f2,res(r0)

    syscall 0

Enable data forwarding mechanism and execute the example program.

Analyze the clock cycle diagram and find the instruction that causes WAR stall.  

Mark the instruction that causes WAR stall.

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Calculate the speedup in relation to the pipelined execution of the program with the DF mechanism disabled.

speedupDF = CPIpip / CPIpipDF

CPIpip value should be taken from Question 30.

What is the speedup value?

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Data Forwarding

A data forwarding (or operand forwarding) mechanism is one of the method to reduce the impact of raw hazards on the pipeline instruction execution. It relies on the existence of additional data paths that allow the results of the instruction execution to be used earlier than after the execution is fully completed. To see how it works, we will use again the example program used for R-A-W hazard investigation.

Before you execute the program in WinMIPS64 simulator, enable the data forwarding mechanism (in Settins  enable the option “CPU forwarding”)

Execute the example program.

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What is the CPI value for pipelined program execution with DF enabled (CPIpipDF)?

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danger brut

L'aléa RAW est l'un des problèmes les plus courants liés à l'exécution pipelinée et parallèle des instructions par le processeur. Ce type d'aléa survient lorsqu'une instruction ultérieure (j) requiert le résultat d'une instruction précédente (i) pour s'exécuter, mais que l'exécution de cette dernière (i) n'est pas encore terminée (fin de la phase WB du cycle d'instruction en MIPS). Si l'exécution du programme n'est pas interrompue, il se peut que l'instruction ultérieure (j) effectue des opérations sur un argument incorrect : la valeur correcte de l'argument de l'instruction (j) n'est pas disponible avant la fin de l'exécution de l'instruction précédente (i). Ce type d'aléa peut être observé lors de l'exécution du programme d'exemple :

;MIPS64 RAW hazard example

    .data

A:    .word 2

B:    .word 3

C:    .word 7

D:    .word 0

    

    .text

main:    ld r1,A(r0)

    ld r2,B(r0)

    dadd r3,r1,r2

    sw r3,C(r0)

    lw r4,C(r0)

    dadd r5,r1,r4

    sw r5,D(r0)

    syscall 0

Analysez ce programme et calculez le nombre de cycles d'horloge nécessaires à son exécution sur le processeur séquentiel. Supposons que l'exécution de chaque instruction prenne 5 cycles d'horloge.

Combien de cycles d'horloge sont nécessaires pour exécuter ce programme sur un processeur séquentiel ?

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Structural hazard

A structural hazard occurs when two or more instructions that are in different phases of the execution request access to the same hardware resource (memory, execution unit, etc.). In MIPS it can be easily observed when you are using the  floating point division unit. The program below can be used to illustrate that situation.

    .data

A:    .word 3

v:    .double

0.0

x:    .double 10.0

y:    .double

5.0

z:    .double 0.0

    

 

  .text

main:        

       LDC1 f2,x(r0)      ;f2=x (ld.d f2,x(r0) )

    LDC1 f3,y(r0)      ;f3=y (ld.d f3,y(r0) )

    

    div.d

f5,f3,f2    ;f5=x/y

    div.d f6,f2,f3  

 ;f6=y/x

    add.d f8,f5,f6  

 ;f8=(x/y)+(y/x)

    

    add.d

f4,f3,f3

    mul.d f7,f13,f2

    mul.d

f13,f2,f4

    mul.d f9,f4,f13

 

  

    SDC1 f8,z(r0)

    SDC1 f9,v(r0)

    syscall 0

Analyze that program and manually calculate how many clock cycles are needed to execute it on a sequential processor. 

Let assume that the execution of any instruction takes 5 clock cycles,

the execution of div.d instruction takes additional 23 clock cycles,

mul.d takes additional 6 clock cycles, add.d takes additional 3 clock cycles.

How many clock cycles are needed to execute this program on a sequential processor?

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Number of clock cycles for pipelined execution

Before you execute the program in WinMIPS64 simulator, disable  the data forwarding mechanism

(in settings at simulation tab disable the option “CPU forwarding”)

Execute the example program with WinMIPS. After the execution is finished answer the question:

What is the number of clock cycles required to execute that program?

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Analyze the clock cycle diagram and find the instruction that causes a structural  stall (StDiv).

Place this instruction into answer box.

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In this section, you will evaluate how long it takes to execute different types of the instructions of the MIPS computer.

Number of clock cycles for dadd instruction (integer addition)

Load and execute in step mode following program:

        .text

main:    dadd

r1,r0,r1 ; r1 = r0+r1 

         nop

         syscall 0

As a result of the execution you should receive clock cycle diagram of the execution similar to this on the image:

Clock cycle diagam of execution of dadd instruction.

Analyze this clock cycle diagram of execution of the program and answer the question: 

How many clock cycles does the execution of the instruction dadd r1,r0,r1 take (each box in clock cycle diagram represents one clock tick )?

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Mark correct sentences:

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