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ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog

ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog

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One way to employ a BIST strategy for logic is as follows:

Turn registers into LFSRS. Run functional vectors through the chip and collect the results as signatures.

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Build registers as scan chains. Generate random vectors off chip, load them in, operate the chip for one cycle and collect the results.

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Turn registers into LFSRs. Alternate their use between producing pseudorandom sequences and collecting a signature. Inspect the signatures for correctness.

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Turn registers into LFSRs. Load random vectors into the logic, and after each cycle load out the observed logic response.

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Which of the following is most true as it applies to design for test (DFT):

Scan-path testing is used to give access to the internal combinational logic from the chip I/O.

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Design of a good DFT strategy is critical to helping you debug the chip before sending it to fabrication.

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Random testing is always preferable to scan path testing.

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Running your verification vectors on your chip to test it will ensure that there are no manufacturing defects in the chip.

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What changes occur in the test sequence when doing delay fault testing?

The internal logic only is run at the normal on-chip clock rate.

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The scan chains only are run at the normal on-chip clock rate.

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Use partial scan.

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The internal logic and the scan chains are run at the normal on-chip clock rate.

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What advantage does SystemVerilog have over Verilog 2001 when it comes to writing assertions?

SystemVerilog permits a briefer syntax.

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SystemVerilog permits assertions to be synthesized.

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SystemVerilog permits assertions to be written as part of a constrained random functional test.

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Assertions can not be written in Verilog 2001.

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When testing memories, it is important to:

Read in all 1s and then all 0s.

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Increase the complexity of the fault model.

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Since memories have Error Correcting Codes, you don’t need to test them.

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Apply pseudorandom vectors.

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If the following logic is built exactly as described, indicate a test vector that sensitizes a stuck-at-1 fault at g and propagates it to the output h. If the value of a particular input does not matter, indicate it as ‘x’ – don’t care.

wire a, b, c, d, e, f, g, h;

assign f = a ? b : c;

assign g = d ^ f;

assign h = e & g;

{a, b, c, d, e} = 10000

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{a, b, c, d, e} = 10101

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{a, b, c, d, e} = 10x01

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{a, b, c, d, e} = 11x01

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If your goal was to maximize performance per unit area, which FPGA design maximizes this metric? Assume a LUT takes four times more area than a register.

Speedup

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Baseline

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What best describes the reason for the need of the command

uniquify -cell U3 -new_name bar2

in a synopsys script?

Allows designware to be mapped to cell bar2

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Permits a hierarchy to be re-partitioned to fix a poor design.

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