Crowdly

{a, b, c, d, e} = 10101

{a, b, c, d, e} = 10x01

{a, b, c, d, e} = 11x01

When testing memories, it is important to:

Read in all 1s and then all 0s.

Increase the complexity of the fault model.

Since memories have Error Correcting Codes, you don’t need to test them.

Apply pseudorandom vectors.

What advantage does SystemVerilog have over Verilog 2001 when it comes to writing assertions?

SystemVerilog permits a briefer syntax.

SystemVerilog permits assertions to be synthesized.

SystemVerilog permits assertions to be written as part of a constrained random functional test.

Assertions can not be written in Verilog 2001.

What changes occur in the test sequence when doing delay fault testing?

The internal logic only is run at the normal on-chip clock rate.

The scan chains only are run at the normal on-chip clock rate.

Use partial scan.

The internal logic and the scan chains are run at the normal on-chip clock rate.

One way to employ a BIST strategy for logic is as follows:

Turn registers into LFSRS. Run functional vectors through the chip and collect the results as signatures.

Build registers as scan chains. Generate random vectors off chip, load them in, operate the chip for one cycle and collect the results.

Turn registers into LFSRs. Alternate their use between producing pseudorandom sequences and collecting a signature. Inspect the signatures for correctness.

Turn registers into LFSRs. Load random vectors into the logic, and after each cycle load out the observed logic response.

primitive PlanetX (A, B);

A D flip-flop

An XOR gate

An AND gate

An OR gate

When might you need to flatten part of a design hierarchy?

When you have a poor partitioning for two of the four modules within this particular hierarchy.

When you have included logic above the leaf modules.

You are having difficulty running characterize on the modules.

What is meant by a “self-checking” test fixture?

It monitors itself for syntax errors.

It keeps track of the outputs and see if they match the expected outputs at the right time.

It runs the assertions inside the synthesized modules.

You have access to a C level model of the chip and your module is clearly identifiable in that C level model. How might you use this model to obtain test vectors and expected outputs for your model. Select all reasonable (i.e. valid) answers.

Obtain vectors from chip level runs with random inputs.

Obtain vectors from chip level runs of actual code and examples.

Use PLI to replace the C description of your module with a Verilog description

Which of these determine what should be placed within one module? There is more than one selection that applies.

The critical path should be contained within the module.

There should be a flip-flop for every path between each input of the module and each output.

Sharable logic should be contained within one procedural block or assign statement.

The design should ensure that all logic is in the leaf cell modules and not specified higher in the hierarchy.