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ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog

ECE 564 (001) Fall 2025 ASIC and FPGA Design with Verilog

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You have access to a C level model of the chip and your module is clearly identifiable in that C level model. How might you use this model to obtain test vectors and expected outputs for your model. Select all reasonable (i.e. valid) answers.

Obtain vectors from chip level runs with random inputs.

✅

Obtain vectors from chip level runs of actual code and examples.

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Use PLI to replace the C description of your module with a Verilog description

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What is meant by code coverage?

Percentage of lines and branches exercised so far in ONE simulation run.

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Percentage of lines and branches exercised so far in accumulated simulation runs.

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Percentage of expected end functions that behave correctly.

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When might you need to flatten part of a design hierarchy?

When you have a poor partitioning for two of the four modules within this particular hierarchy.

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When you have included logic above the leaf modules.

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You are having difficulty running characterize on the modules.

❌

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What is meant by a “self-checking” test fixture?

It monitors itself for syntax errors.

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It keeps track of the outputs and see if they match the expected outputs at the right time.

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It runs the assertions inside the synthesized modules.

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In a hierarchical design, when you run the first compile command in the script, what exactly is synthesized?

The entire design is flattened and synthesized.

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The sub-hierarchy specified by current_design is flattened and synthesized.

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None of the above

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The design is synthesized one module at a time for the sub-hierarchy specified by current_design.

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The entire design is synthesized one module at a time.

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Is there any “glue logic” (logic not part of a module) in top_without_mem iin the motion estimator exampl.e

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Yes

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After executing the following code, what is the value of f002 in U0.

module top();

parameter Gfoo = 2**3;

foobar #(.foo2(Gfoo)) U0 (.clock(clock));

endmodule

module foobar (.clock(clock));

parameter foo1=4;

parameter foo2=16;

…

endmodule

✅

❌

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In the motion estimator we first spent some effort determining the speed of the critical path. Why?

This step was not actually necessary.

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So that we could work out a clock period.

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Since the throughput was fixed, this was needed so we could determine the how many of these units we needed in parallel.

✅

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Why does the motion estimator have a hierarchy level described top_without_mem ?

To make sure there was no glue logic in top.

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Memories are not produced by synthesis. Thus we need that part of the design without memories. It is best to pass one (hierarchical) module to synthesis.

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Top also includes the test fixture.

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Why is the motion estimator controller implemented as a decoded counter?

A Mealy machine would actually be faster.

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It goes through a fixed sequence of steps without any variations. Though it could be coded as an FSM, this is the simplest way to think about it.

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A Moore machine would actually be faster.

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