module fubar1 (input clock, input [1:0] H, input [2:0] B, output reg A, C);

always@(H) A = ^H;

always@(B) A=|B;

fubar2 u1 (clock, H, C);

endmodule

 What is wrong with the following code fragment. More than one thing might be wrong. You lose answers for an incorrect choice.

Note, this is the entire module - there is no additional code

module fubar1 (input clock, input [1:0] H, input [2:0] B; output wire A);

 integer i;

 always@(B, H)

 begin

 A = 0;

 for (i=0; i<=H; i=i+1)

if (B[i]) A=!A;

end

endmodule

For a research project, you have a choice of using an FPGA or using a standard cell design. However, you still will need to compare design performance, density and power compared with other designs implemented in the same technology. The wiring pattern in the high level architecture is as below. This wiring pattern is unique to your design. The buses shown are also very wide – 64 bits. Which best matches your reasoning as to which platform you will choose and why?

Consider the following hardware, built exactly as described. Determine a test vector that that tests for a SA-0 fault at node B and propagates the fault to the register C. In that test vector A[1] should be 0. Write your answer as a 3-digit string. E.g. if the answer is A[2]=1, A[1]=1, A[0]=x, then write 11x without any spaces or quotes.

reg [2:0] A;

reg B, C, D;

always@(*)

begin

B = A[2] | A[1];

D = A [1] ^ A[0];

End

always@(posedge clock)

C = B & D;

You are designing a prototype network security system. Your analysis indicates you could use a 100 MHz design with a total of 10M logic gates, or a 1 GHz design with a total of 1M logic gates. However, you don’t have a lot of budget and you expect the design to have frequent revisions. Which implementation style do you choose?

You are designing a packet forwarding engine for a network router. To process each packet you have to do eight SRAM reads in sequence and one random DRAM read. Packets come in on a continuous basis – there is little dead time. The off-chip DRAM takes 60 ns to do a random access. You have these choices for the on-chip SRAM

1. A two-port (one read, one write) 10 ns SRAM

2. A three-port (two read, one write) 15 ns SRAM

3. Repeat the data in two two-port (one read, one write) 10 ns SRAMs

Which would you choose to maximize the performance per unit of area?

Consider the following blocking code example.

always@(posedge clock)

begin

A = B;

B = A;

D = C;

C = B;

end

Which of the following code fragments using blocking assignment will result in the same logic structure.   

Consider the the following codes exactly as described. Which is likely to give the lowest overall power consumption if E is high for only 10% of the clock cycles but A and B change on 90% of the clock cycles. For this question assume that the energy per operation is as follows:

• Adder = 50 fJ

• Register with enable = 10 fJ

• Mux = 5 fJ

You are having difficulty meeting setup timing.  What are some of the viable options available to you.  More than one option might be viable.  By "viable" I mean have a high chance of helping.

Both of these questions apply to the following code implemented exactly as described.

module A1 (input clock, E, F; output reg A, B);

wire C

always@(posedge clock)

   begin

    A <= C;

    B <= F;

   end

assign C = E | F;

endmodule

Each gate has a delay from its input to output as given as {1 : 2 : 3}, t_Cp_Q is {2 : 3 : 5} the clock skew is 1 ns, the flip-flop setup time is 1 ns and the hold time 1 ns.  Format above is {min : typical : max}. 

This module is part of a hierarchy 

     A1 U1 (clock, E, F, A, B);

     A2 U2 (clock, G, H, E, F);

A2 is another module with a clock two inputs and two outputs.  If you were synthesizing A2 by itself, (i.e. A1 is not being synthesized in the same run) what vales should be assigned for  the  output delay for the ports of module A2.  Ignore any interconnect delay.

 Give your answers as integers

 Output delay