What individual parameter ranges might you expect to see possibly contribute to a timing corner being used to evaluate setup violations?  More than one applies.  Points are taken off for incorrect selections.

Consider the following timing diagram. There are only two states in the FSM, S0 and S1. Design an FSM that is consistent with this timing diagram. Combinational logic delays are not included in this timing diagram.

always@(*)

case (current_state)

S0: // complete the code for S0

S1: // complete the code for S1

endcase

always@(posedge clock)

if (Reset) current_state = S0;

else current_state = next_state;

Write an assertion in Verilog 95 that checks that a particular bus CHANGES every clock cycle and does not take the value xx or zz. I.e. changes to and from xx or zz are errors. E.g. The change from xx to 80 is flagged as an error but no error is reported below when 80 changes to 03. E.g. Reports errors as follows. [10 points]

The overall structure is

//synopsys off

‘ifdef Assertions_on

Your code goes here

‘endif

// synopsys on

You have an 8 entry 16-bit wide register file. It contains signed numbers. You are designing a piece of combinational logic that determines the number of negative numbers in the register file. Capture the logic as a FOR loop. The following are some other fragments from the code. Bit 15 is the sign bit.

Hint if A is declared as

reg [31:0] A [0:7];

then A[i][j] is the j’th bit of the I’th vector in the array.

reg [15:0] RegisterFile [0:7];

integer i;

reg [3:0] NegativeCount;

Write a single continuous assignment statement that takes an 8 bit signed integer number and multiplies it by two, preserving the sign bit. Use Verilog 95 syntax, not Verilog 2001 syntax. Do not use *. [5 points]

input [7:0] In;

wire [7:0] out;

You are designing an engine that modifies packets in a stream. The incoming packets on “In” are 8 bits of content. The packets you will produce on “Out” have 8 bits of content and a 9^th parity bit. You are to use odd parity. Each packet is to appear THREE clock cyles after In changes and with the correct parity. An example is given below. All values are in Hex.

The module header is given below.

module exam (input clock, input [7:0] In, output reg [8:0] out);

write the rest of the module. This question is worth double the normal question at 10 points. Declare all variables. Make sure the module is complete and syntactically correct.

Consider the following logic exactly as described. Note the use of a latch. Cycle stealing is not enabled.

always@(clock)

begin

if (clock) A <= B;

if (clock) B <= A ^ C;

if (clock) C <= B;

end

This is synthesized with the following commands

Create_clock –name clock period 10 –waveform 0 5

Set_clock_uncertainty 1 clock

Note, t_ck-Q-min = 2 ns; t_hold=1 ns; t_su=0 ns; t_logic = 1 ns;

Is there potential for hold violations? If so what is the margin?

Of what type must A be declared within module top?

module top;

foobar u1 (.E(B), .A(A));

endmodule

module foobar (input [3:0] E; output A);

always@(*)

A = |E;

endmodule

Is the following code fragment syntheziable?

 Parameter loopcount=4;

 reg A;

reg [7:0] B;

 always@(*)

begin

A = 0;

for (i=0; i<=loopcount;i=i+1) if (B[i]) A = 1;  

end