What is wrong with the following code fragment?

always@(posedge clock)

   begin

    D <= A & G;

    if (E) G <= D | F;

   end

Generally, you would use an FSM over a counter in a controller when…

What best describes the purpose of the command replace_synthetic –ungroup in our standard class synopsys script?

Why is the main reason why I recommended avoiding using latches in this class?

What does the following primitive describe:

primitive PlanetX (A, B);

output F;

reg F;

input A, B;

table

0 0 : 0

0 1 : 1

1 1 : 1

1 0 : 1

endtable

endprimitive

Consider the following code implemented exactly as described.

always@(posedge clock)

   begin

    A <= B;

    B <= F;

    E <= H;

  end

assign C = A ^ B;

assign F = C | E;

assign H = F | A;

Each gate has a delay from its input to output as given as {1 : 2 : 3}, t_Cp_Q is {3 : 4 : 5} the clock skew is 1 ns, the flip-flop setup time is 1 ns and the hold time 2 ns.  Format above is {min : typical : max}.

Is there potential for a hold violation in this logic?

Consider the following code implemented exactly as described.

always@(posedge clock)

   begin

    A <= B;

    B <= F;

    E <= H;

  end

assign C = A ^ B;

assign F = C | E;

assign H = F | A;

Each gate has a delay from its input to output as given as {1 : 2 : 3}, t_Cp_Q is {3 : 4 : 5} the clock skew is 1 ns, the flip-flop setup time is 1 ns and the hold time 2 ns.  Format above is {min : typical : max}.

The fastest possible viable clock period is:

 If the following logic is built exactly as described, which test vector sensitizes a stuck-at-0 fault at e and propagates it to the output g.

wire a, b, c, d, e, f, g;

assign e = a & b;

assign f = c ^ e;

assign g = d | f;

If  “enable” is high only 10% of the time, and the code below is synthesized, which of the following will have the lowest power consumption.  

Consider the following code fragment.  Notice the use of non-blocking assignment.

always@(posedge clock)

begin

  B <= A^C;

  C <= B;

end

Which BLOCKING code version would lead to identical logic (after any potential logic gate sharing is taken into account)?